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Si4322
CONTROL INTERFACE
Commands to the receiver are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on pin
SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. The number of bits sent
is an integer multiple of 8. All commands consist of a command code, followed by a varying number of parameter or data bits. All data
are sent MSB first (e.g. bit 15 for a 16-bit command). Bits having no influence (don’t care) are indicated with X. The Power On Reset
(POR) circuit sets default values in all control registers.
The receiver will generate an interrupt request (IRQ) for the microcontroller on the following events:
? Supply voltage below the preprogrammed value is detected (LBD)
? Wake-up timer timeout (WK-UP)
? FIFO received the preprogrammed amount of bits (FFIT)
? FIFO overflow (FFOV)
FFIT and FFOV are applicable only when the FIFO is enabled. To find out why the nIRQ was issued, the status bits should be read out.
Timing Specification
Symbol
t CH
t CL
t SS
t SH
t SHI
t DS
t DH
t OD
Timing Diagram
t SS
nSEL
Parameter
Clock high time
Clock low time
Select setup time (nSEL falling edge to SCK rising edge)
Select hold time (SCK falling edge to nSEL rising edge)
Select high time
Data setup time (SDI transition to SCK rising edge)
Data hold time (SCK rising edge to SDI transition)
Data delay time
Minimum value [ns]
25
25
10
10
25
5
5
10
t SHI
t CH
t CL
t OD
t SH
SCK
t DS
t DH
SDI
SDO
BIT15
BIT15
BIT14
BIT14
BIT13
BIT13
BIT8
BIT8
BIT7
BIT7
BIT1
BIT1
BIT0
BIT0
8
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